The present invention relates in general to the manufacture of integrated circuits, and in particular relates to spacer films used in semiconductor devices.
Semiconductor devices such as a metal oxide semiconductor field effect transistors (MOSFETs) are known in the art. P-type FETs (PFETs) or n-type FETs (NFETs) are often formed using very different dopant species. These species have very different physical properties such as diffusion rate and maximum activated concentration. A spacer is used to define the edge for the source-drain implants for a FET device. When a voltage is applied at the gate and the channel under the gate oxide is active, there is flow of electrical carriers from the source to the drain.
The use of dual spacers has been described, for example by Fung et al. (co-assigned U.S. patent application Ser. No. 10/277,907, filed on Oct. 21, 2002, to the same assignee as the present application), which is incorporated by reference herein in its entirety, to optimize the performance of different MOS devices, e.g. NFET or PFET device performance, independently on the same substrate. In the example of dual spacers, where the spacer width next to poly gate conductor on the PFET device is different from the spacer width next to the poly gate conductor on the NFET device. This kind of spacer can also be called an asymmetric spacer. In this device construction, the spacer width on the PFET is greater than the width on the NFET by almost a factor or 2, i.e., for an NFET spacer width of 40 nm, the corresponding PFET spacer is about 80 nm in width. The PFET spacer is larger since it usually is in relation to the implant species that is used in the source-drain region that typically contains boron. When the implant species are activated through the source-drain activation anneal, the large spacer on the PFET helps in defining the appropriate edge for the implant profile for the source-drain regions. The thinner spacer width on the NFET is designed to maximize the device performance.
A variety of different silicon nitride films can be used to define the spacer, which is part of the first processing step towards forming a spacer. Conventionally, a high temperature furnace silicon nitride could be deposited, or if the thermal budget from a furnace operation is deemed excessive, a rapid thermal processed silicon nitride film is deposited using a chemical vapor deposition (RTCVD) method. The typical temperature for an RTCVD film is about 700° C. to 800° C., for a process deposition time less than 5 minutes per wafer, more typically between about 2 to 3 minutes. However, the temperatures used in RTCVD processing may still exceed the thermal budget for the device. Other methods to deposit silicon nitride films at lower process temperatures of 400° to 500° C. are known using plasma enhanced CVD techniques (PECVD), where the plasma plays a critical role in achieving the formation and deposition of silicon nitride films on the substrate. However, the conventional technique of using a PECVD film suffers from a serious conformality problem, that is, the film is uniform when deposited on near-planar substrate features but has uneven thickness when features with different aspect ratio are present.
For example, by the time the spacers are to be formed to make a semiconductor device, the gate poly conductor is typically patterned. The width of the poly conductor lines would be typically between 300 Å to 800 ÅA, and height of the poly conductor line is typically in the order of 1000 Å to 2000 Å. Referring to FIG. 1, a substrate 10 is illustrated, having polysilicon lines 20. The deposition thickness of the silicon nitride layer 30 would vary along different regions. The poly conductor (PC) line 20 is the feature over which the spacer needs to be deposited and shaped. Region A of the silicon nitride layer 30 denotes the planar region 31 overlying the substrate 10; region B of the nitride layer 30 denotes the portion overlying the top surface 21 of the PC line; C denotes the region of the nitride layer 30 covering the vertical side well 22 of the PC line; region D denotes the transition region of the nitride layer from to vertical sidewall region C to the planar horizontal region A of the nitride layer 30. Typically for a PECVD silicon nitride tUna, the thickness on vertical sidewall C is about 30 to 80% of the thickness of the planar region A, depending on the aspect ratio. For forming a spacer and using it to define as a device, the transitional region D is of great importance. The transition region D of the nitride layer 30 should be continuous and without seams. The thickness and uniformity of transition region D would vaxy based on the aspect ratio of the PC line 20. The two big problems for PECVD silicon nitxide filnis for spacer applications is the poor confonnality (less than 50% ) and the presence of seams 43 (which may be observed from subsequent wet cleans that are used to form cobalt silicide junction Contacts to the source-drain regions).
There is, therefore, a need for a method of forming nitride spacers that have improved conformality and uniformity (i.e., absence of seams).